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TDA7561
MULTIFUNCTION QUAD POWER AMPLIFIER WITH BUILT-IN DIAGNOSTICS FEATURES
s s s s
s s s s s
DMOS POWER OUTPUT HIGH OUTPUT POWER CAPABILITY 4x25W/ 4W @ 14.4V, 1KHZ, 10% THD, 4x35W EIAJ MAX. OUTPUT POWER 4x60W/2W FULL I2C BUS DRIVING: - ST-BY - INDEPENDENT FRONT/REAR SOFT PLAY/ MUTE - SELECTABLE GAIN 26dB - 12dB (FOR LOW NOISE LINE OUTPUT FUNCTION) - I2C BUS DIGITAL DIAGNOSTICS FULL FAULT PROTECTION DC OFFSET DETECTION FOUR INDEPENDENT SHORT CIRCUIT PROTECTION CLIPPING DETECTOR ESD PROTECTION
MULTIPOWER BCD TECHNOLOGY MOSFET OUTPUT POWER STAGE
FLEXIWATT25
DESCRIPTION The TDA7561 is a new BCD technology QUAD BRIDGE type of car radio amplifier in Flexiwatt25 BLOCK DIAGRAM
CLK DATA
package specially intended for car radio applications. Thanks to the DMOS output stage the TDA7561 has a very low distortion allowing a clear powerful sound.This device is equipped with a full diagnostics array that communicates the status of each speaker through the I2C bus.The possibility to control the configuration and behaviour of the device by means of the I2C bus makes TDA7561 a very flexible machine.
VCC1
VCC2
CD_OUT
REFERENCE
THERMAL PROTECTION & DUMP
I2C BUS MUTE1 MUTE2
CLIP DETECTOR
IN RF
F OUT RF+ 12/26dB OUT RFR SHORT CIRCUIT PROTECTION & DIAGNOSTIC OUT RR+ 12/26dB OUT RRF SHORT CIRCUIT PROTECTION & DIAGNOSTIC OUT LF+ 12/26dB OUT LFR SHORT CIRCUIT PROTECTION & DIAGNOSTIC OUT LR+ 12/26dB OUT LRSHORT CIRCUIT PROTECTION & DIAGNOSTIC SVR
D00AU1229
IN RR
IN LF
IN LR
AC_GND
RF
RR
LF
LR
TAB PW_GND
S_GND
December 2002
1/19
TDA7561
ABSOLUTE MAXIMUM RATINGS
Symbol Vop VS Vpeak VCK VDATA IO IO Ptot Tstg, Tj Operating Supply Voltage DC Supply Voltage Peak Supply Voltage (for t = 50ms) CK pin Voltage Data Pin Voltage Output Peak Current (not repetitive t = 100ms) Output Peak Current (repetitive f > 10Hz) Power Dissipation Tcase = 70C Storage and Junction Temperature Parameter Value 18 28 50 6 6 8 6 85 -55 to 150 Unit V V V V V A A W C
THERMAL DATA
Symbol Rth j-case Parameter Thermal Resistance Junction to case Max. Value 1 Unit C
PIN CONNECTION
25 24 23 22 DATA PW_GND RR OUT RRCK OUT RR+ 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 VCC2 OUT RFPW_GND RF OUT RF+ AC GND IN RF IN RR S GND IN LR IN LF SVR OUT LF+ PW_GND LF OUT LFVCC1 OUT LR+ 4 3 2 1 CD-OUT OUT LRPW_GND LR TAB
D99AU1037
2/19
TDA7561
Figure 1. Test and Application Circuit
C8 0.1F
C7 3300F Vcc1 6 Vcc2 20 17 18 19 + OUT RR + OUT LF + OUT LR TAB + OUT RF
DATA I2C BUS CLK C1 0.22F IN RF C2 0.22F IN RR C3 0.22F IN LF C4 0.22F IN LR S-GND
25
22
21 24 23 9 8 7
15
14
11
5 2
12
3
13
16
10
4
1
47K C5 1F C6 10F CD OUT V
D00AU1212
3/19
TDA7561
ELECTRICAL CHARACTERISTCS (Refer to the test circuit, VS = 14.4V; RL = 4; f = 1KHz;Tamb = 25C; unless otherwise specified).
Symbol POWER AMPLIFIER VS Supply Voltage Range Total Quiescent Drain Current Output Power EIAJ (VS = 13.7V) THD = 10% THD = 1% RL = 2; EIAJ (VS = 13.7V) RL = 2; THD 10% RL = 2; THD 1% RL = 2; MAX POWER THD Total Harmonic Distortion 50 32 32 22 8 150 35 25 20 55 38 30 60 0.04 0.02 50 80 25 -1 11 -1 Rg = 600, 20Hz to 22kHz Rg = 600; GV = 12dB 20Hz to 22kHz f = 100Hz to 10kHz; Vr = 1Vpk; Rg = 600 50 100 90 110 25 80 Mute & Play -100 7 D2/D1 (IB1) 0 to 1 D2/D1 (IB1) 1 to 0 100 0 7.5 20 20 100 8 40 40 100 35 12 60 12 60 100 26 130 27 1 13 1 80 20 0.1 0.05 18 300 V mA W W W W W W W % % dB K dB dB dB dB V V dB KHz dB A dB mV V ms ms Parameter Test Condition Min. Typ. Max. Unit
Id
PO
PO = 1W to 10W;
GV = 12dB; VO = 0.1 to 5VRMS
CT RIN GV1 GV1 GV2 GV2 EIN1 EIN2 SVR BW ASB ISB AM VOS VAM TON TOFF
Cross Talk Input Impedance Voltage Gain 1 Voltage Gain Match 1 Voltage Gain 2 Voltage Gain Match 2 Output Noise Voltage 1 Output Noise Voltage 2 Supply Voltage Rejection Power Bandwidth Stand-by Attenuation Stand-by Current Mute Attenuation Offset Voltage Min. Supply Mute Threshold Turn on Delay Turn off Delay
f = 1KHz to 10KHz, RG = 600
4/19
TDA7561
ELECTRICAL CHARACTERISTCS (continued) (Refer to the test circuit, VS = 14.4V; RL = 4; f = 1KHz;Tamb = 25C; unless otherwise specified).
Symbol CDLK CDSAT CDTHD Parameter Clip Det High Leakage Current Clip Det Sat. Voltage Clip Det THD level CD off CD on; ICD = 1mA Test Condition Min. Typ. 0 150 1 Max. 15 300 2 Unit A mV %
TURN ON DIAGNOSTICS 1 (Power Amplifier Mode) Pgnd Short to GND det. (below this limit, the Output is considered in Short Circuit to GND) Short to Vs det. (above this limit, the Output isconsidered in Short Circuit to VS) Normal operation thresholds. (Within these limits, the Output is considered without faults). Shorted Load det. Open Load det. Normal Load det. 130 1.5 70 Power Amplifier in st-by condition 1.2 V
Pvs
Vs -1.2
V
Pnop
1.8
Vs -1.8
V
Lsc Lop Lnop
0.5

TURN ON DIAGNOSTICS 2 (Line Driver Mode) Pgnd Short to GND det. (below this limit, the Output is considered in Short Circuit to GND) Short to Vs det. (above this limit, the Output isconsidered in Short Circuit to VS) Normal operation thresholds. (Within these limits, the Output is considered without faults). Shorted Load det. Open Load det. Normal Load det. 400 4.5 200 Power Amplifier in st-by 1.2 V
Pvs
Vs -1.2
V
Pnop
1.8
Vs -1.8
V
Lsc Lop Lnop
1.5
& & &
PERMANENT DIAGNOSTICS 2 (Power Amplifier Mode or Line Driver Mode) Pgnd Short to GND det. (below this limit, the Output is considered in Short Circuit to GND) Short to Vs det. (above this limit, the Output is considered in Short Circuit to VS) Normal operation thresholds. (Within these limits, the Output is considered without faults) Power Amplifier in Mute or Play, one or more short circuits protection activated Vs -1.2 1.2 V
Pvs
V
Pnop
1.8
Vs -1.8
V
5/19
TDA7561
ELECTRICAL CHARACTERISTCS (continued) (Refer to the test circuit, VS = 14.4V; RL = 4; f = 1KHz;Tamb = 25C; unless otherwise specified).
Symbol LSC Parameter Shorted Load det. Test Condition Power Amplifier mode Line Driver mode VO Offset Detection Power Amplifier in play, AC Input signals = 0 1.5 2 Min. Typ. Max. 0.5 1.5 2.5 Unit V
I2C BUS INTERFACE fSCL VIL VIH Clock Frequency Input Low Voltage Input High Voltage 2.3 400 1.5 KHz V V
Figure 2. Quiescent Current vs. Supply Voltage
Id (mA) 250 230 210 190 170 150 130 110 90 70 50 8 10 12 Vs (V) 14 16 18 Vin = 0 NO LOADS
Figure 4. Output Power vs. Supply Voltage (4)
Po (W) 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 8
Po-max RL = 2 Ohm f = 1 KHz THD= 10 %
THD= 1 %
9
10
11
12 Vs (V)
13
14
15
16
Figure 3. Output Power vs. Supply Voltage (2)
Po (W) 70 65 60 55 50 45 40 35 30 25 20 15 10 5 8 9 10 11 12 13 Vs (V) 14 15 16 17 18 THD= 1 % RL = 4 Ohm f = 1 KHz THD= 10 % Po-max
Figure 5. Distortion vs. Output Power (2)
THD (%) 10
Vs = 14.4 V RL = 4 Ohm 1
f = 10 KHz 0.1 f = 1 KHz
0.01 0.1
1 Po (W)
10
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TDA7561
Figure 6. Distortion vs. Output Power (2)
THD (%) 10
90 80
Figure 9. Crosstalk vs. Frequency
CROSSTALK (dB)
Vs = 14.4 V RL = 2 Ohm 1
70 60
f = 10 KHz
50
0.1
f = 1 KHz
40 30
Vs = 14.4 V RL = 4 Ohm Po = 4 W Rg = 600 Ohm
0.01 0.1
1 Po (W)
10
20 10
100
f (Hz)
1000
10000
Figure 7. Distortion vs. Frequency (4)
THD (%) 10 Vs = 14.4 V RL = 4 Ohm Po = 4 W 1
Figure 10. Supply Voltage Rejection vs.Frequency
SVR (dB) 90 80 70 60 50
0.1
40 30
0.01 10 100 1000 10000
Rg = 600 Ohm Vripple = 1 Vpk
f (Hz)
20 10
100
f (Hz)
1000
10000
Figure 8. Distortion vs. Frequency (2)
THD (%) 10 Vs = 14.4 V RL = 2 Ohm Po = 8 W 1
Figure 11. Power Dissipation & Efficiency vs.Output Power (4, SINE)
Ptot (W) 90 80 70 60 50 Ptot 40 40 30 20 10 0 26 Vs = 14.4 V RL = 4x4 Ohm f= 1 KHz SINE n n (%) 90 80 70 60 50
0.1
30 20 10
0.01 10
100 f (Hz)
1000
10000
0 0 2 4 6 8 10 12 14 Po (W) 16 18 20 22 24
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TDA7561
Figure 12. Power Dissipation vs. Average Ouput Power (Audio Program Simulation, 4)
Ptot (W) 45 40 35 30 25
40 90 80
Figure 13. Power Dissipation vs. Average Ouput Power (Audio Program Simulation, 2)
Ptot (W)
Vs = 14.4 V RL = 4x4 Ohm GAUSSIAN NOISE
70
CLIP START
60 50
Vs = 14.4 V RL = 4x2 Ohm GAUSSIAN NOISE
CLIP START
20 15 10 5 0 1 2 Po (W) 3 4 5
30 20 10 0 0 1 2 3 4 Po (W) 5 6 7 8
DIAGNOSTICS FUNCTIONAL DESCRIPTION: a) TURN-ON DIAGNOSTIC. It is activated at the turn-on (stand-by out) under I2Cbus request. Detectable output faults are: - SHORT TO GND - SHORT TO Vs - SHORT ACROSS THE SPEAKER - OPEN SPEAKER To verify if any of the above misconnections are in place, a subsonic (inaudible) current pulse (fig. 14) is internally generated, sent through the speaker(s) and sunk back.The Turn On diagnostic status is internally stored until a successive diagnostic pulse is requested (after a I2C reading). If the "stand-by out" and "diag. enable" commands are both given through a single programming step, the pulse takes place first (power stage still in stand-by mode, low, outputs = high impedance). Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The previous Turn On state is kept until a short appears at the outputs. Figure 14. Turn - On diagnostic: working principle
Vs~5V Isource
I (mA) Isource Isink
CH+ CH-
Isink
~100ms Measure time
t (ms)
8/19
TDA7561
Fig. 15 and 16 show SVR and OUTPUT waveforms at the turn-on (stand-by out) with and without TURN-ON DIAGNOSTIC. Figure 15. SVR and Output behaviour (CASE 1: without turn-on diagnostic)
Vsvr Out
Permanent diagnostic acquisition time (100mS Typ)
Bias (power amp turn-on)
Diagnostic Enable (Permanent)
t
FAULT event
Permanent Diagnostics data (output) permitted time
Read Data
I2CB DATA
Figure 16. SVR and Output pin behaviour (CASE 2: with turn-on diagnostic)
V s vr Out
Tu rn - o n d i a g n o s t ic a c q u is itio n tim e (1 0 0 m S Typ ) P e r m a n e n t d ia g n o s tic a c q u i s itio n tim e (1 0 0 m S Ty p )
t
D ia g n o s tic E n a b le (Tu r n -o n ) Tu r n - o n D ia g n o s tic s d a ta (o u t p u t) p e rm itt e d ti m e D ia g n o s tic E n a b l e (P e rm a n e n t )
FA U LT e v e nt
B ia s (p o w e r a m p t u rn -o n ) p e r m i tte d t im e
R e a d D a ta
P e r m a n e n t D ia g n o s t ic s d a ta (o u tp u t ) p e r m itt e d t im e
I2 C B D ATA
The information related to the outputs status is read and memorized at the end of the current pulse top. The acquisition time is 100 ms (typ.). No audible noise is generated in the process. As for SHORT TO GND / Vs the fault-detection thresholds remain unchanged from 26 dB to 12 dB gain setting. They are as follows:
S.C. to GND
x
Normal Operation
x
S.C. to Vs
0V
1.2V
1.8V
VS-1.8V
VS-1.2V
D01AU1253
VS
9/19
TDA7561
Concerning SHORT ACROSS THE SPEAKER / OPEN SPEAKER, the threshold varies from 26 dB to 12 dB gain setting, since different loads are expected (either normal speaker's impedance or high impedance). The values in case of 26 dB gain are as follows:
S.C. across Load
x
Normal Operation
x
Open Load
0V
0.5
1.5
70
130
D01AU1254
Infinite
If the Line-Driver mode (Gv= 12 dB and Line Driver Mode diagnostic = 1) is selected, the same thresholds will change as follows:
S.C. across Load
x
Normal Operation
x
Open Load
0
1.5
4.5
200
400
D01AU1252
infinite
b) PERMANENT DIAGNOSTICS. Detectable conventional faults are: - SHORT TO GND - SHORT TO Vs - SHORT ACROSS THE SPEAKER The following additional features are provided: - OUTPUT OFFSET DETECTION The TDA7561 has 2 operating statuses: 1) RESTART mode. The diagnostic is not enabled. Each audio channel operates independently from each other. If any of the a.m. faults occurs, only the channel(s) interested is shut down. A check of the output status is made every 1 ms (fig. 17). Restart takes place when the overload is removed. 2) DIAGNOSTIC mode. It is enabled via I2C bus and self activates if an output overload (such to cause the intervention of the short-circuit protection) occurs to the speakers outputs . Once activated, the diagnostics procedure develops as follows (fig. 18): - To avoid momentary re-circulation spikes from giving erroneous diagnostics, a check of the output status is made after 1ms: if normal situation (no overloads) is detected, the diagnostic is not performed and the channel returns back active. - Instead, if an overload is detected during the check after 1 ms, then a diagnostic cycle having a duration of about 100 ms is started. - After a diagnostic cycle, the audio channel interested by the fault is switched to RESTART mode. The relevant data are stored inside the device and can be read by the microprocessor. When one cycle has terminated, the next one is activated by an I2C reading. This is to ensure continuous diagnostics throughout the car-radio operating time. - To check the status of the device a sampling system is needed. The timing is chosen at microprocessor level (over half a second is recommended).
10/19
TDA7561
Figure 17. Restart timing without Diagnostic Enable (Permanent) Each 1mS time, a sampling of the fault is done
Out
1-2mS 1mS 1mS 1mS 1mS
t
Overcurrent and short circuit protection intervention (i.e. short circuit to GND) Short circuit removed
Figure 18. Restart timing with Diagnostic Enable (Permanent)
1mS 100mS 1mS 1mS
t
Overcurrent and short Short circuit removed (i.e. short circuit to GND)
OUTPUT DC OFFSET DETECTION. Any DC output offset exceeding 2V are signalled out. This inconvenient might occur as a consequence of initially defective or aged and worn-out input capacitors feeding a DC component to the inputs, so putting the speakers at risk of overheating. This diagnostic has to be performed with low-level output AC signal (or Vin = 0). The test is run with selectable time duration by microprocessor (from a "start" to a "stop" command):START = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1STOP = Actual reading operation Excess offset is signalled out if persistent throughout the assigned testing time. This feature is disabled if any overloads leading to activation of the short-circuit protection occurs in the process. MULTIPLE FAULTS. When more misconnections are simultaneously in place at the audio outputs, it is guaranteed that at least one of them is initially read out. The others are notified after successive cycles of I2C reading and faults removal, provided that the diagnostic is enabled. This is true for both kinds of diagnostic (Turn on and Permanent). The table below shows all the couples of possible double-fault. It should be taken into account that a short circuit with the 4 ohm speaker unconnected is considered as double fault. Double fault table for Turn On Diagnostic
S. GND (so) S. GND (so) S. GND (sk) S. Vs S. Across L. Open L. S. GND / / / / S. GND (sk) S. GND S. GND / / / S. Vs S. Vs + S. GND S. Vs S. Vs / / S. Across L. S. GND S. GND S. Vs S. Across L. / Open L. S. GND Open L. (*) S. Vs N.A. Open L. (*)
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TDA7561
S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2 outputs is shorted to ground (test-current source side= so, test-current sink side = sk). More precisely, so = CH+, sk = CH-. In Permanent Diagnostic the table is the same, with only a difference concerning Open Load(*) , which is not among the recognisable faults. Should an Open Load be present during the device's normal working, it would be detected at a subsequent Turn on Diagnostic cycle (i.e. at the successive Car Radio Turn on). FAULTS AVAILABILITY All the results coming from I2Cbus, by read operations, are the consequence of measurements inside a defined period of time. If the fault is stable throughout the whole period, it will be sent out. To guarantee always resident functions, every kind of diagnostic cycles (Turn on, Permanent, Offset) will be reactivate after any I2C reading operation. So, when the micro reads the I2C, a new cycle will be able to start, but the read data will come from the previous diag. cycle (i.e. The device is in Turn On state, with a short to Gnd, then the short is removed and micro reads I2C. The short to Gnd is still present in bytes, because it is the result of the previous cycle. If another I2C reading operation occurs, the bytes do not show the short). In general to observe a change in Diagnostic bytes, two I2C reading operations are necessary. I2C PROGRAMMING/READING SEQUENCE A correct turn on/off sequence respectful of the diagnostic timings and producing no audible noises could be as follows (after battery connection): TURN-ON: (STAND-BY OUT + DIAG ENABLE) --- 500 ms (min) --- MUTING OUT TURN-OFF: MUTING IN --- 20 ms --- (DIAG DISABLE + STAND-BY IN) Car Radio Installation: DIAG ENABLE (write) --- 200 ms --- I2C read (repeat until All faults disappear). OFFSET TEST: Device in Play (no signal) -- OFFSET ENABLE - 30ms - I2C reading (repeat I2C reading until high-offset message disappears).
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7561 and viceversa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown by fig. 19, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown by fig. 20 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
12/19
TDA7561
Acknowledge The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 21). The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDAline is stable LOW during this clock pulse. * Transmitter = master (P) when it writes an address to the TDA7561 = slave (TDA7561) when the P reads a data byte from TDA7561 ** Receiver = slave (TDA7561) when the P writes an address to the TDA7561 = master (P) when it reads a data byte from TDA7561 Figure 19. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 20. Timing Diagram on the I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 21. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
13/19
TDA7561
SOFTWARE SPECIFICATIONS All the functions of the TDA7561 are activated by I2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from P to TDA7561) or read instruction (from TDA7561 to P). Chip Address:
D7 1 1 0 1 1 0 0 D0 X D8 Hex
X = 0 Write to device X = 1 Read from device If R/W = 0, the mP sends 2 "Instruction Bytes": IB1 and IB2. IB1
D7 D6 D5 X Diagnostic enable (D6 = 1) Diagnostic defeat (D6 = 0) Offset Detection enable (D5 = 1) Offset Detection defeat (D5 = 0) Front Channel Gain = 26dB (D4 = 0) Gain = 12dB (D4 = 1) Rear Channel Gain = 26dB (D3 = 0) Gain = 12dB (D3 = 1) Mute front channels (D2 = 0) Unmute front channels (D2 = 1) Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) X
D4
D3
D2 D1 D0
IB2
D7 D6 D5 D4 D3 D2 D1 D0 X used for testing used for testing Stand-by on - Amplifier not working - (D4 = 0) Stand-by off - Amplifier working - (D4 = 1) Power amplifier mode diagnostic (D3 = 0) Line driver mode diagnostic (D3 = 1) X X X
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TDA7561
If R/W = 1, the TDA7561 sends 4 "Diagnostics Bytes" to P: DB1, DB2, DB3 and DB4. DB1
D7 D6 D5 D4 Thermal Warning active (D7 = 1) Diag. cycle not activated or not terminated (D6 = 0) Diag. cycle terminated (D6 = 1) X Channel LFTurn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) Channel LF Normal load (D3 = 0) Short load (D3 = 1) Channel LFTurn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Offset diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) Channel LFNo short to Vcc (D1 = 0)Short to Vcc (D1 = 1) Channel LFNo short to GND (D1 = 0)Short to GND (D1 = 1)
D3
D2
D1 D0
DB2
D7 D6 D5 D4 D3 Offset detection not activated (D7 = 0) Offset detection activated (D7 = 1) X X Channel LRTurn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) Channel LRNormal load (D3 = 0) Short load (D3 = 1) Channel LRTurn-on diag.: No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) Channel LR No short to Vcc (D1 = 0) Short to Vcc (D1 = 1) Channel LR No short to GND (D1 = 0) Short to GND (D1 = 1)
D2
D1
D0
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TDA7561
DB3
D7 D6 D5 D4 D3 Stand-by status (= IB1 - D4) Diagnostic status (= IB1 - D6) X Channel RFTurn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) Channel RFNormal load (D3 = 0) Short load (D3 = 1) Channel RF Turn-on diag.: D2
No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) Channel RFNo short to Vcc (D1 = 0) Short to Vcc (D1 = 1) Channel RFNo short to GND (D1 = 0) Short to GND (D1 = 1)
D1 D0
DB4 D7 D6 D5 D4 X X X Channel RR Turn-on diagnostic (D4 = 0) Permanent diagnostic (D4 = 1) Channel RR Normal load (D3 = 0) Short load (D3 = 1) Channel RR Turn-on diag.: D2
D3
No open load (D2 = 0) Open load detection (D2 = 1) Permanent diag.: No output offset (D2 = 0) Output offset detection (D2 = 1) Channel RRNo short to Vcc (D1 = 0)Short to Vcc (D1 = 1) Channel RRNo short to GND (D1 = 0)Short to GND (D1 = 1)
D1 D0
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TDA7561
Examples of bytes sequence 1 - Turn-On diagnostic - Write operation
Start Address byte with D0 = 0 ACK IB1 with D6 = 1 ACK IB2 ACK STOP
2 - Turn-On diagnostic - Read operation
Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK DB3 ACK DB4 ACK STOP
The delay from 1 to 2 can be selected by software, starting from T.B.D. ms 3a - Turn-On of the power amplifier with 26dB gain, mute on, diagnostic defeat.
Start Address byte with D0 = 0 ACK IB1 X000000X ACK IB2 XXX1X0XX ACK STOP
3b - Turn-Off of the power amplifier
Start Address byte with D0 = 0 ACK IB1 X0XXXXXX ACK IB2 XXX0XXXX ACK STOP
4 - Offset detection procedure enable
Start Address byte with D0 = 0 ACK IB1 XX1XX11X ACK IB2 XXX1X0XX ACK STOP
5 - Offset detection procedure stop and reading operation (the results are valid only for the offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4).
Start
s
Address byte with D0 = 1
ACK
DB1
ACK
DB2
ACK
DB3
ACK
DB4
ACK
STOP
The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input capacitor with anomalous leackage current or humidity between pins. The delay from 4 to 5 can be selected by software, starting from T.B.D. ms
s
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TDA7561
mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 24.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 0.945 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019
DIM. A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3
MIN. 4.45 1.80 0.75 0.37 0.80 23.75 28.90
MAX. 4.65 2.00 1.05 0.42 0.57 1.20 24.25 29.30
MIN. 0.175 0.070 0.029 0.014 0.031 0.935 1.138
MAX. 0.183 0.079 0.041 0.016 0.022 0.047 0.955 1.153
OUTLINE AND MECHANICAL DATA
22.07 18.57 15.50 7.70
22.87 19.37 15.90 7.95
0.869 0.731 0.610 0.303
0.904 0.762 0.626 0.313
3.70 3.60
4.30 4.40
0.145 0.142
0.169 0.173
5 (Typ.) 3 (Typ.) 20 (Typ.) 45 (Typ.)
Flexiwatt25
(1): dam-bar protusion not included (2): molding protusion included
V3 H3
H H1 H2 R3 R4 V1 R2 R L L1 A
L4
O
L2
N
L3
V1
V2
R2 L5 G V B C V
FLEX25ME
R1 R1 R1 E
D
G1
F M M1
18/19
TDA7561
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
(R)
19/19

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